The present invention relates generally to non-volatile memory cells and in particular the present invention relates to flash memory cells.
Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicate a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write.
Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. The transistors can be erased to restore the threshold voltage of the transistor. The memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. These non-volatile memory devices are commonly referred to as flash memories.
The non-volatile memory cells are fabricated as floating gate memory cells and include a source region and a drain region that is laterally spaced apart from the source region to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and is can also made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is xe2x80x9cfloatingxe2x80x9d in dielectric so that it is insulated from both the channel and the control gate.
As semiconductor devices get smaller in size, designers are faced with problems associated with the production of memory cells that consume a small enough amount of surface area to meet design criteria, yet maintain sufficient performance in spite of this smaller size.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved non-volatile memory cell.
The above-mentioned problems with non-volatile memory cells and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory cell comprises a substrate, source and drain regions located in the substrate and vertically spaced apart to define a vertical channel region, a floating gate located horizontally adjacent the channel region, and a vertically extending control gate located adjacent to the floating gate.
In another embodiment, a non-volatile memory cell comprises a substrate, source and drain regions located in the substrate and vertically spaced apart to define a vertical channel region, a floating gate located horizontally adjacent the channel region, a control gate located adjacent to the floating gate and extending in Y and Z directions, and a word line coupled to the control gate, wherein the word line extends in an X direction perpendicular to the control gate.
A method of fabricating a floating gate transistor comprises fabricating first and second laterally spaced trenches in a substrate, such that a vertically extending substrate island is formed. A source region is implanted under the first and second trenches and in the substrate. The method further comprises implanting a drain region in a top region of the substrate island, fabricating a first dielectric layer adjacent to the substrate island, and fabricating a floating gate adjacent to the first dielectric layer such that the first dielectric layer is between the floating gate and the substrate island. A second dielectric layer is fabricated adjacent to the floating gate, and a control gate is fabricated adjacent to the second dielectric layer such that the second dielectric layer is between the control gate and the floating gate.